An ATD circuit for electronic memory devices typically includes a plurality of input pads of the memory device each one connected to a corresponding address input buffer, with each input buffer comprising an output terminal connected to a corresponding input of a local Address Transition Detection (ATD) generator circuit. An output for each local generator is connected to a corresponding input of a logic gate having a plurality of inputs and an output.
As is well known, an electronic memory device may be provided with an ATD circuit which is used to detect any address transition on the address inputs of the memory device and to output a pulse output signal which activates a read operation of the memory device. More specifically, the output signal of the ATD circuit is used to generate a sequence of signals which take care of and control the read operation.
In many applications a known ATD circuit provides a negative pulse which is generated every time an address transition is detected and is interrupted after a predetermined time delay Tatd from the last detected address transition. If we assume that a time delay Td is present between the first detected address transition and the falling edge of the ATD pulse, the ATD circuit should guarantee a minimum width Tpmin of the ATD pulse. This is given by the following relationship: EQU Tpmin=Tatd-Td
with Tp.gtoreq.Tpmin
The enclosed FIG. 1 shows a graphic representation of these time delays. The enclosed FIG. 2 shows a simplified schematic diagram of a known ATD circuit.
As may be appreciated from FIG. 2, a plurality of input pads A&lt;0&gt;, . . . , A&lt;N&gt; of the memory device represent an array of address inputs each of which is connected to a corresponding address input buffer I0, . . . , IN. Each input buffer comprises an output terminal connected to a corresponding input of an ATD generator circuit ATD.sub.-- GEN.sub.-- LOC.
The single output of each ATD generator is connected to an input of a NOR logic gate having N inputs and an output Y. An optional STRETCH circuit may be connected to this output Y. In response to an address transition on one pad A&lt;i&gt;, the corresponding ATD generator produces a positive pulse ATD.sub.-- LOC.sub.-- X which generates a negative pulse ATDBUS on the output of the NOR gate. The STRETCH circuit is used to increase the length of the ATDBUS pulse producing the ATD signal.
As a matter of fact, other input signals (i.e. the signal CE) of the memory device can contribute to the ATD generation. However, their contribution will not be considered in the following description since it is not relevant for the comprehension of the inventive principle.
The enclosed FIG. 3 shows a simplified internal structure of an ATD generator circuit ATD.sub.-- GEN.sub.-- LOC of a known type. FIG. 4 shows a typical STRETCH circuit used to delay the rising edge of the signal ATDBUS. The STRETCH circuit is substantially formed by a delay chain of logic gates.
It may happen that the above indicated ATD circuit is not able to respond in a proper way when it is stimulated by a glitch. Glitches may be observed on the address inputs due to the noise on the internal power supply and because of the noise on the input level. A set of FIGS. 5a, 5b, 5c, 5d, 5e show how the above indicated known ATD circuitry responds to an address input transition, and to a glitch, respectively. The response depends on the extent of the glitch.
It may be observed in FIGS. 5c and 5d respectively that, under some critical conditions, the known ATD circuitry might provide an ATD pulse whose duration is shorter than a conventional one. More specifically, FIG. 5c shows a situation in which the ATDBUS pulse is shorter than a conventional pulse of that kind, but the STRETCH circuit is still able to increase the duration of its input signal.
On the contrary, FIG. 5d shows a worst case in which the ATDBUS pulse is so short that the STRETCH circuit is not able to respond in a proper way and a final very short ATD pulse is produced. In many applications it is mandatory to guarantee an ATD pulse having a minimum width Tpmin under every operating condition.
FIG. 6 shows a simplified block diagram of the read path of a non-volatile memory circuit using dynamic sense amplifiers. In this figure the signal ATD is presented to the input of a SENSING.sub.-- CONTROL circuit which provides the sequence of signals to control the sensing operation. In response to the falling edge of the ATD pulse, the SENSING.sub.-- CONTROL circuit generates a Y.sub.-- GATE.sub.-- EN signal which enables the bitline selection of the memory device. In response to the rising edge of the ATD pulse the SENSING.sub.-- CONTROL circuit provides a sequence of signals to time the sensing operation. As can be easily understood, if the duration of the ATD pulse is shorter than expected, the result of the sensing operation may be wrong since the right timing between the bit line selection and the sensing phase is missing.
For example, after a normal read cycle the noise produced by the internal power supplies due to the output transitioning can trigger a glitch on the input to the ATD circuit. This can generate a spurious ATD pulse thereby starting a new read cycle. In such a case, the memory location of the previous read operation is read again, but the data output remains stable so that the user would not realize the double read operation.
However, if the glitch produces an ATD pulse of very short duration, the corresponding read operation might fail giving a wrong data output as a result. Therefore, a user would observe a failing read operation. In a memory device using static sense amplifiers, the above situations do not cause a failing read operation but might determine a push-out of the access time.